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Today’s trends
Past 24 hours
Focus Shifts to Physical Constraints and Infrastructure for AI Growth
The collected feed highlights both the rapid advancement of AI models and the critical physical limitations confronting this growth. There is a clear emphasis on infrastructure, with discussions pointing out that securing large-scale power supply and robust hardware foundations are becoming as crucial as raw computing power itself. While major tech players and advanced model development remain highly visible, market coverage shows divergence: while big tech stocks hit record highs, the semiconductor and infrastructure sectors face downward pressure due to political uncertainty and local resistance.
Growing Concerns Over AI Code Quality and Security
The feed has recently focused heavily on the advancements of AI agents and the new challenges they introduce to software development. There is a noticeable technical effort to ensure output reliability, seen in tools like 'depgraph' for detecting latent code debt from AI-generated code or the use of adaptive ensemble methods (COVE) for pre-validating LLM outputs. Furthermore, alongside predictions that AI agents will evolve to autonomously manage aspects of human life, there is a concurrent warning about escalating security risks and infrastructure vulnerabilities, indicating significant uncertainty.
RuC: Rule-Agnostic Code Completion Benchmark Generation for HDL
This paper proposes the 'Rule-agnostic Code Completion (RuC)' framework to overcome limitations in existing code completion benchmarks as Large Language Models (LLMs) are integrated into Register Transfer Level (RTL) development. RuC is a grammar-based, rule-selectable benchmark generator that automatically creates RTL code completion tasks from input Hardware Description Language (HDL) source code sets, allowing for precise evaluation of LLM performance across various scopes.
Key takeaways
RuC (Rule-agnostic Code Completion) is a novel benchmark generation framework designed for HDL-based RTL development.
It overcomes the limitations of existing benchmarks regarding granularity and grammar scope control.
RuC enhances evaluation precision by requiring models to reconstruct code in masked areas while utilizing surrounding context.
Experimental results demonstrate that LLM completion performance heavily depends on the prompting strategy (e.g., Fill-in-the-Middle) and the grammatical structure of the masking area.
NeuroRing: Scaling Spiking Neural Networks via Multi-FPGA Bidirectional Ring Topology and Stream-Dataflow Architecture
NeuroRing is a modular FPGA-based platform that accelerates large-scale Spiking Neural Networks (SNNs) by combining stream-dataflow architecture with a bidirectional ring topology. The system offers excellent scalability, being programmable via High-Level Synthesis (HLS) and supporting both single or multi-FPGA deployments. Benchmarks show NeuroRing achieves execution speeds faster than real-time and demonstrates superior energy efficiency, proving its flexible application in both neuroscience simulations and event-based applications.
Key takeaways
Adopted stream-dataflow architecture and bidirectional ring topology to solve SNN scalability issues.
Implemented on programmable FPGAs using High-Level Synthesis (HLS), supporting modular and multi-FPGA deployment.
Demonstrated execution speeds faster than real-time and excellent energy efficiency in cortical microcircuits and Sudoku tasks.
High compatibility with existing NEST simulator workflows, allowing easy integration into neuroscience research.
AHASD: Asynchronous Heterogeneous Architecture for Adaptive Speculative Decoding in Mobile LLM Inference
This paper proposes AHASD, a novel asynchronous heterogeneous architecture designed to enhance Large Language Model (LLM) inference efficiency via adaptive speculative decoding on mobile NPU-PIM systems. AHASD minimizes resource waste by separating DLM and TLM at the task level for parallel speculation generation in PIM, while integrating entropy-history recognition and time-aware pre-verification control. Experimental results demonstrate high performance, achieving up to 4.2x throughput improvement and 5.6x energy efficiency gain compared to existing GPU-only baselines.
Key takeaways
Proposes AHASD, an adaptive speculative decoding architecture based on mobile NPU-PIM systems.
Designed for parallel speculation generation in PIM by separating DLM and TLM at the task level.
Minimizes resource waste using a dynamic speculative control mechanism integrating entropy and time awareness.
Maximizes task switching speed by integrating attention units and gated scheduling units into LPDDR5-PIM.
Achieves up to 4.2x throughput and 5.6x energy efficiency improvement compared to GPU-only systems.
llm
speculative decoding
npu-pim
heterogeneous architecture
mobile computing
arXivAI-generated brief
Multi-bit Neural Inference in N-ary Crossbar Architecture
This paper presents a simulation framework for performing energy-efficient neural network inference using In-Memory Computing (IMC) on an N-ary crossbar architecture. The researchers successfully performed XOR and MNIST classification using a 4-state Self-Tunnel Junction (MTJ) crossbar array, achieving high performance compared to software baselines. They analyzed weight quantization as the primary source of error and studied the effects of random noise and systematic non-idealities to derive the optimal number of states per cell that minimizes total MVM error.
Key takeaways
N-ary crossbar architectures enable energy-efficient neural network inference through IMC.
A 4-state MTJ crossbar array simulation achieved an accuracy of 94.48% on MNIST classification.
Weight quantization error was identified as the main cause of performance degradation and its impact was analyzed.
Cell-level random noise has less influence than systematic non-idealities, leading to a proposed optimal setting for states per cell.
BZL's Comprehensive V&V-in-the-Loop for RISC-V Design
Barcelona Zeta Scale Lab (BZL) proposes a comprehensive Verification and Validation (V&V) methodology for high-performance computing chip designs based on RISC-V. This approach integrates three complementary platforms: UVM-based RTL verification, an FPGA-based system-level hardware-software validation platform, and a CI/CD flow for continuous automation.
Key takeaways
BZL establishes a comprehensive V&V methodology for high-performance computing chip designs using RISC-V.
The proposed V&V approach consists of three core platforms: UVM-based RTL verification, FPGA-based system-level hardware-software validation, and CI/CD automation.
This integrated loop provides a robust and scalable development environment that ensures the functional accuracy and system-level validation of RISC-V chip designs.
The BZL project aims to contribute to strengthening Europe's strategic capabilities in hardware and computing.
SafeTune: Mitigating Data Poisoning in LLM-Generated RTL Code
SafeTune is a framework designed to counter data poisoning attacks that can occur when Large Language Models (LLMs) generate hardware code, such as Register Transfer Level (RTL). It significantly enhances the robustness and reliability of LLM-based RTL generation by integrating structural knowledge via Graph Neural Networks (GNNs) with semantic validation using text embeddings and XGBoost classifiers.
Key takeaways
The use of LLMs for generating hardware code (RTL) increases the risk of 'data poisoning attacks' due to insufficient security verification in training datasets.
The SafeTune framework aims to make LLM-based RTL generation robust against data poisoning attacks.
Key components include ① Graph Neural Networks (GNNs) for identifying anomalous patterns and ② a validation module for semantic security assessment.
SafeTune combines structural knowledge and semantic knowledge, allowing it to effectively filter out poisoned inputs without losing valuable data.
EMiX: Multi-FPGA Simulation Beyond Single Chip Limits
EMiX is a scalable multi-FPGA framework designed to simulate large-scale multi-core RISC-V architectures by overcoming the resource limitations of a single FPGA. This platform achieves high scalability and performance by systematically partitioning monolithic designs across multiple interconnected FPGAs, successfully demonstrating a 64-core system running Linux using eight Alveo U55c FPGAs.
Key takeaways
EMiX is a distributed simulation framework for multi-core RISC-V that surpasses single FPGA resource limits.
It systematically partitions monolithic designs into components deployed across multiple interconnected FPGAs.
Scalability and performance are maintained by utilizing effective interconnections between FPGAs without requiring RTL redesign.
A 64-core architecture was prototyped using eight Alveo U55c FPGAs, successfully demonstrating Linux booting.
The PvE survival game *Windrose* generates abnormally high disk I/O during gameplay, placing stress on SSD longevity. Specifically, character movement or ship operation can continuously read and write data at 15–30 MB/s, potentially leading to excessive write traffic up to 108 GB per hour, which has been mitigated by a new patch from developer Kraken Express.
Key takeaways
*Windrose* causes excessive SSD load due to high-frequency disk read/writes during gameplay.
This I/O pattern is particularly risky for QLC or older SSDs.
The game's storage system uses RocksDB, generating high write traffic due to small WAL budgets and frequent flush/compaction processes.
A new patch has significantly reduced disk usage, allowing for more stable gameplay.
AWS Becoming an OEM, Similar to Google and Microsoft
Major cloud service providers (AWS, Azure, Google Cloud) function as de facto Original Equipment Manufacturers (OEMs), offering integrated stacks while preserving customer optionality. However, AI companies and large corporations are increasingly favoring owning and operating hardware in their own data centers for better cost control and efficiency.
Key takeaways
Major cloud providers act as OEMs, achieving vertical integration while maintaining horizontal option for customers.
AI firms and large enterprises are trending toward On-premise ownership of hardware to ensure cost savings and greater control.
Google demonstrated this shift by allowing Anthropic to install TPU racks within its own data center, moving away from a pure 'rental' model.
Due to the high cost of AI computing infrastructure, companies are entering into long-term, large-scale purchase agreements (e.g., $10 billion deals).
Analysts Project Big Tech's 2026 CAPEX Spending to Hit $725 Billion
Major big tech companies, including Google, Microsoft, Meta, and Amazon, are expected to significantly increase their Capital Expenditure (CAPEX) in 2026 to a total of $725 billion compared to the previous year. This surge is attributed to explosive cloud service growth and intensifying competition in building AI infrastructure, leading major firms to raise their CAPEX guidelines due to rising costs for memory chips and data center construction.
Key takeaways
Due to intense AI infrastructure competition among big tech companies, total 2026 CAPEX spending is projected to reach $725 billion, representing an increase of approximately 77% year-over-year.
Google showed the strongest growth with cloud revenue ($20B) and raised its Alphabet CAPEX guideline to $190B.
Microsoft and Meta set high CAPEX estimates citing rising costs for memory chips and data center construction, anticipating continued supply constraints for infrastructure like GPUs/CPUs.
Google demonstrated a competitive advantage by achieving a faster growth rate in the cloud market compared to Amazon and Microsoft.
Investors are noting the transformation of big tech from capital-light models to highly capital-intensive infrastructure build-out structures.
bigtech
capex
ai-infrastructure
cloud-computing
google
Tom's HardwareAI-generated brief
Cloud Provider Recovers Data After AI Agent Deletion Error
A serious incident occurred where a critical database was accidentally deleted by an AI coding agent, but the cloud provider, Railway, successfully recovered the data. Following this event, Railway significantly improved overall system security and stability by implementing a 48-hour soft delete feature for all deletion operations, including API calls, and strengthening instant undo capabilities.
Key takeaways
The risk of an AI agent accidentally deleting critical operational data was proven through a real-world incident.
Following the data loss event, the cloud provider (Railway) introduced 48-hour soft delete and instant undo features for all deletion operations, including API calls.
New guardrails and reassessments of granular token permissions were established to account for future AI agent usage environments.
Cloud services must now be designed so that agents access them through user-friendly interfaces rather than raw API endpoints, making them accessible not only to engineers but also to non-experts.
Samsung and SK Hynix Warn of Persistent Memory Shortage Due to AI Demand
Samsung Electronics and SK Hynix warned that severe supply shortages across memory products could persist until 2027, driven by the massive demand for HBM (High-Bandwidth Memory) required for AI infrastructure. This shortage stems from the rapidly growing AI accelerator market, forcing manufacturers to concentrate resources on high-profit AI memory while impacting the supply of traditional DRAM used in servers, PCs, and mobile devices.
Key takeaways
The surging demand for HBM (High-Bandwidth Memory), essential for building AI infrastructure, is acting as the primary cause of a core shortage in the memory market.
Major suppliers like Samsung Electronics and SK Hynix have warned of severe, multi-year memory shortages attributed to the rapid growth of the AI accelerator market.
Manufacturers face the risk that concentrating resources on high-profit HBM production will tighten the supply of existing DRAM products for servers, PCs, and mobile devices.
While the industry is exploring next-generation technologies like 3D X-DRAM and ZAM to improve power efficiency, current demand remains overwhelmingly focused on existing memory technologies.
AI Data Centers Strain Electrical Labor Market in Texas
The rapid construction boom of AI data centers and their massive power needs are overloading the electrical labor market in Texas, causing severe delays for housing and other projects. Hyperscalers are monopolizing skilled electricians with high wages, leaving general contractors struggling with shortages and project delays up to two months.
Key takeaways
AI data center construction is creating a severe labor shortage for residential and general construction by absorbing skilled electricians.
Hyperscalers gain an advantage over small-to-medium contractors by offering high salaries and benefits to specialized electricians.
The allocation of 45–70% of data center budgets to power work has caused a surge in demand for skilled electricians.
Due to labor shortages and power grid constraints, housing projects are delayed up to two months, affecting data center construction as well.
Chinese GPU Makers Accelerate AI Chip Market Growth, Challenging Nvidia's Dominance
Major Chinese GPU designers Cambricon and MetaX reported strong quarterly earnings, demonstrating rapid growth in China's domestic AI chip market. These companies are emerging as core players in the government-approved supply chain, successfully absorbing market share previously held by Nvidia due to US sanctions.
Key takeaways
Chinese semiconductor companies are rapidly replacing Nvidia's market share in China (Nvidia's share reduced to less than 60%).
Cambricon showed strong growth, recording significant year-over-year increases in revenue and net profit, moving from losses to first-time annual profits.
Both Cambricon and MetaX are key players in the domestic AI hardware supply chain, included in major procurement lists approved by the Chinese government.
Market demand is being driven primarily by large tech companies such as ByteDance and Alibaba, who are emerging as major purchasers.
DIY DualSense Adapter for PC: Restoring Haptics and Triggers
The DS5Dongle project addresses the issue of missing adaptive triggers and haptic feedback when using a Sony DualSense controller wirelessly on PC. This device can be built for under $20 using low-cost components like the Raspberry Pi Pico 2W, functioning by receiving Bluetooth data and 'handshaking spoofing' it to the PC as if wired.
Key takeaways
The DS5Dongle solves the loss of adaptive triggers and haptic feedback when connecting DualSense controllers wirelessly to PC.
The device can be built for under $20 using low-cost components such as the Raspberry Pi Pico 2W.
It operates by receiving data via Bluetooth and employing a 'handshake spoof' method, making it appear wired to the PC.
User reports indicate that the device maintains low latency, providing a wireless gaming experience similar to PS5, almost indistinguishable from wired play.
The Governor of Tennessee signed a bill banning the use of cryptocurrency ATMs (Crypto ATM) effective July 1, 2026. This makes Tennessee the second state to implement such restrictions, following Indiana's action. The state government is limiting these machines to prevent further financial losses, as the FBI has warned that Crypto ATMs have been exploited by fraudsters, causing Americans to lose substantial amounts of money.
Key takeaways
Tennessee signed a bill banning the use of Crypto ATMs in response to increasing fraud risks.
This regulation is the second state-level measure of its kind, following Indiana's action.
The FBI warned that Crypto ATMs have been misused as fraud tools, leading to significant financial losses for Americans.
Funds deposited into Crypto ATMs are often difficult or impossible for victims to recover, complicating victim protection.
Multi-Programming for Surface-Code Architecture in FTQC
This paper addresses complex multi-programming challenges within Fault-Tolerant Quantum Computing (FTQC) environments. Because FTQC involves structured resource floorplans—such as data, annealer, and magic state services—the problem is significantly more complicated than simple qubit pool division. The researchers developed a formal framework that captures these structural constraints and runtime effects, leading to substantial improvements in system speed and performance during simulated Clifford+T workloads.
Key takeaways
FTQC multi-programming requires considering structured resource placement (data, annealer, magic state) rather than just simple qubit pool division.
The proposed formal framework enables optimal resource allocation by capturing structural constraints and runtime impacts.
The framework extends from static assignment problems to online environments via a hierarchical-aware scheduling policy.
Simulation results show that the proposed scheduler improves system speed by 3.1 times and enhances performance by approximately 29% compared to existing baselines.
AMMA: Memory-Centric Architecture for Low-Latency 1M Context Attention Serving
AMMA is a multi-chiplet, memory-centric architecture proposed to solve the memory-bound attention bottleneck encountered in ultra-long context (1M token) environments. By replacing computing dies with an HBM-PNM cube and introducing optimized microarchitectures and parallelization schemes, AMMA achieves significantly lower attention latency and energy consumption compared to existing GPU-centric designs.
Key takeaways
Existing LLM serving systems are inefficient for long-context memory-bound workloads due to their reliance on GPU-centric design.
AMMA adopts a memory-centric architecture by replacing computing dies with an HBM-PNM cube, thereby maximizing memory bandwidth utilization.
The system introduces logic microarchitectures and a two-stage hybrid parallelization scheme for internal bandwidth optimization under minimum power and area budgets.
AMMA demonstrated superior performance compared to NVIDIA H100, achieving 15.5x improvement in attention latency and 6.9x improvement in energy consumption.
RAG-Enhanced Kernel-Based Heuristic Synthesis (RKHS) for Large Language Models
This paper proposes RAG-Enhanced Kernel-Based Heuristic Synthesis (RKHS), a novel method allowing Large Language Models (LLMs) to systematically synthesize reusable optimization heuristics beyond simple code generation. RKHS enhances LLM performance by integrating Retrieval Augmented Generation (RAG), compact kernel templates, and a self-feedback loop, demonstrating its effectiveness in minimizing latency list scheduling for High-Level Synthesis (HLS).
Key takeaways
Presents a methodology to systematically synthesize complex optimization heuristics in the Electronic Design Automation (EDA) field using LLMs.
The proposed RKHS combines RAG, kernel templates, and an iterative self-feedback loop to strengthen LLM-based synthesis.
Demonstrated performance includes up to an 11% reduction in average schedule length compared to existing methods for HLS latency minimization list scheduling prototypes.
The structured search-synthesis loop shows high generalizability potential for other EDA optimization problems.
Sparse-on-Dense: Area and Energy Efficient Computation of Sparse Neural Networks in Dense Matrix Multiplication Accelerators
As deep neural networks (DNNs) grow larger, they create high computational complexity and memory requirements, leading to the use of sparse neural networks via pruning. Previous dedicated sparse accelerators faced area and power efficiency issues due to index matching circuits. This paper proposes an area and energy-efficient method for performing sparse network operations by using a dense matrix multiplication hardware accelerator (Sparse-on-Dense) to solve these problems.
Key takeaways
The increasing size of DNNs results in high computational complexity and memory footprint issues.
Pruning is an effective method for reducing the computational complexity of DNNs.
Traditional sparse accelerators faced difficulties regarding area and power efficiency due to index matching circuits.
This study proposes improving area and energy efficiency by performing sparse neural network operations using dense matrix multiplication hardware (Sparse-on-Dense).